Device and method for detecting alignment of deep trench capacitors and word lines in DRAM devices

ABSTRACT

A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to test devices, and more particularly, toa test device for detecting alignment of deep trench capacitors and wordlines in DRAM devices with vertical transistors, as well as a testmethod thereof.

2. Description of the Related Art

With the wide application of integrated circuits (ICs), several kinds ofsemiconductor devices with higher efficiency and lower cost arepresently produced based on different objectives, making DRAM animportant semiconductor device in the information and electronicsindustry.

Most DRAM carries one transistor and one capacitor in a single DRAMcell. The memory capacity of the DRAM can reach 256 megabits. Therefore,with increased integration it is necessary to reduce the size of memorycells and transistors to accommodate DRAM with higher memory capacityand processing speed. A 3-D capacitor structure can itself reduceoccupation area in the semiconductor substrate, such as with a deeptrench capacitor, and is applied to the fabrication of the DRAM of 64megabits and above.

As compared with a traditional plane transistor, however, this structurecovers many areas of the semiconductor substrate and cannot satisfy thedemands of high integration. Therefore, a vertical transistor which cansave space is important in structuring memory unit.

FIG. 1 is a cross section of a conventional memory device with verticaltransistors, and FIG. 2 is a layout of the conventional memory device asshown in FIG. 1. The adjacent memory cells may experience currentleakage and cell failure, reducing process yield, if word line masks anddeep trench capacitors are not aligned accurately. Therefore, processyield and reliability of the memory cells can be improved if alignmentaccuracy between the masks of word lines and the deep trench capacitorsis controlled within an acceptable range.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to detect alignmentof word lines and deep trench capacitors in DRAM devices.

According to the above mentioned object, the present invention providesa test device and method for detecting alignment of word lines and deeptrench capacitors in DRAM devices with vertical transistors.

In the test device of the present invention, an active area is disposedin the scribe line region. An H-type deep trench capacitor is disposedin the active area, and has parallel first and second portions and athird portion. Each first and second portion has a center and two ends.The third portion is disposed between the centers of the first andsecond portions. First to fourth conductive pads are disposed on the twoends of the first and second portions respectively. A bar-typeconductive pad is disposed between the first and second portions, havinga center aligned with a center of the third portion.

According to the present invention, a method for detecting alignment ofdeep trench capacitors and word lines in DRAM devices with verticaltransistors includes the following steps. First, a wafer with at leastone scribe line region and at least one memory region is provided. Then,a plurality of memory cells in the memory region and at least one testdevice in the scribe line region are formed simultaneously, wherein thememory cells have word lines and deep trench capacitors. A firstresistance between the first conductive pad disposed on the firstportion and the bar-type conductive pad is detected. A second resistancebetween the second conductive pad disposed on the second portion and thebar-type conductive pad is detected. Next, alignment of the H-type deeptrench capacitor and the bar-type conductive pad is determined accordingto the first resistance and the second resistance. Finally, alignment ofthe deep trench capacitors and word lines in the memory regions isdetermined according to alignment of the H-type deep trench capacitorand the bar-type conductive pad of the test device.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by the subsequentdetailed description and examples with reference made to theaccompanying drawings, wherein:

FIG. 1 is a cross section of a conventional memory device with verticaltransistors;

FIG. 2 is a layout of the conventional memory device as shown in FIG. 1;

FIG. 3 a is a layout of the test device according to the presentinvention; and

FIG. 3 b is an equivalent diagram of the test device according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

In the present invention, at least one test device 200 is formed in thescribe line region, while a plurality of memory cells with verticaltransistors is formed in the memory regions on a wafer simultaneously.The test device 200 is shown in FIG. 3 a, and a plurality of memorycells formed in the memory region is shown in FIG. 1 and FIG. 2.

As shown in FIG. 1, deep trench capacitors 102 are formed into a matrixand disposed in the substrate 100. Each deep trench capacitor 102includes a top electrode 102 a, an isolation layer 102 b, and a storageelectrode 102 c, and has a vertical transistor 104 disposed thereon.Each vertical transistor 104 includes a gate 104 a, a gate oxide layer104 b, a source 104 c and a common drain 104 d. The gate oxide layer 104b is the sidewall at the bottom of the gate 104 a, and the verticalregion between the source 104 c and the common drain 104 d in thesubstrate 100 is the channel of the transistor 104. In addition, anisolation layer 108 and an ion diffusion layer 106 are disposed betweenthe gate 104 a and the top electrode 102 a of the deep trench capacitor102. The sidewall of the isolation layer 108 is the source 104 c, andthe isolation layer 108 is disposed between the gate 104 a and the iondiffusion layer 106 for electrical insulation.

As shown in FIG. 2, word lines 118 a, 118 b, 118 c and 118 d aredisposed above the active area 112 as the gate 104 a of the transistor104. Command drains 104 d are disposed above the active areas 112between adjacent word lines 118 a and 118 b or 118 c and 118 d. Bitlines 116 a and 116 b are perpendicular to word lines 118 a˜118 d, andare electrically coupled to the command drains through bit line contacts114.

FIG. 3 a is a layout of the test device of the present invention. Thetest device 200 detects the alignment of word lines and deep trenchcapacitors in DRAM devices with vertical transistors, wherein the testdevice 200 is disposed in a scribe line region of a wafer (not shown).

In test device 200 shown in FIG. 3, an active area A₁ is disposed in thescribe line region (not shown) and an H-type deep trench capacitor (D₁₁,D₁₂ and D₂₁) is disposed in the active area. The H-type has parallelfirst and second portions (D₁₁ and D₁₂) and a third portion (D₂₁),wherein each of the first and second portions (D₁₁ and D₁₂) has a centerand two ends, and the third portion D₂₁ is disposed between the centersof the first and second portions (D₁₁ and D₁₂). First to fourthconductive pads (P₁˜P₄) are disposed on the two ends of the first andsecond portions (D₁₁ and D₁₂) respectively. A bar-type conductive padP₅₁ is disposed between the first and second portions (D₁₁ and D₁₂), andhas a center aligned with a center of the third portion D21.

In the present invention, active areas 112 in the memory region and anactive area A₁ in the scribe line region are formed simultaneously withthe same process and conditions.

The deep trench capacitors 102 of the memory cells in the memory regionand an H-type deep trench capacitor (D₁₁, D₁₂ and D₂₁) in the activearea A₁ are formed simultaneously with the same masks, process andconditions. The H-type deep trench capacitor has a first portion D₁₁, asecond portion D₁₂ and a third portion D₂₁. The first and secondportions D₁₁ and D₁₂ are parallel, and the third portion D₂₁ is disposedbetween the centers of the first and second portions D₁₁ and D₁₂. Thefirst, second and third portions D₁₁, D₁₂ and D₂₁ all have the samewidth W.

The word lines 118 a˜118 b (as the gates of the vertical transistors104) of the memory cells in the memory regions and the first to fourthconductive pads P₁˜P₄ and the bar-type conductive pad P₅₁ are formedsimultaneously with the same masks, process and conditions. The firstand third conductive pads P₁ and P₃ are disposed on the two ends of thefirst portions D₁₁ respectively. The second and fourth conductive padsP₂ and P₄ are disposed on the two ends of the second portions D₁₂respectively. The bar-type conductive pad P₅₁ is disposed between thefirst and second portions (D₁₁ and D₁₂), and has a center aligned with acenter of the third portion D₂₁. The bar-type conductive pad P₅₁ isparallel to the first and second potions D₁₁ and D₁₂, and perpendicularto the third portion D₂₁. The bar-type conductive pad P₅₁ is thedistances L−ΔL and L+ΔL from the first portion D₁₁ and the secondportion D₁₂ respectively. The first to fourth conductive pads and thebar-type conductive pad are made of the same material, such aspolysilicon.

FIG. 3 b is an equivalent diagram of the test device according to thepresent invention. Normally, a first resistance R₁ between the firstconductive pad P₁ and the bar-type conductive pad P₅₁ can be detected. Asecond resistance between the first conductive pad P₂ and the bar-typeconductive pad P₅₁ can be detected. The first resistance R₁ and thesecond resistance R₂ can be obtained according to equations 1 and 2.$\begin{matrix}{{R_{1} = {R_{DT} \times \frac{L - {\Delta\quad L}}{W}}};} & (1) \\{{R_{2} = {R_{DT} \times \frac{L + {\Delta\quad L}}{W}}};} & (2)\end{matrix}$

Wherein R_(DT) is the resistance per surface area of the H-type deeptrench capacitor (D₁₁, D₁₂ and D₂₁), W is the width of the first portionD₁₁, the second portion D₁₂ and the third portion D₂₁, L−ΔL is thedistance between the bar-type conductive pad P₅₁ and the first portionD₁₁, and L+ΔL is the distance between the bar-type conductive pad P₅₁and the second portion D₁₂. Use of the same process, material andconditions, equations 3 and 4 can be achieved according to the equations1 and 2. $\begin{matrix}{{{\frac{R_{1}}{R_{2}} = \frac{L - {\Delta\quad L}}{L + {\Delta\quad L}}};}\quad} & (3) \\{{{\Delta\quad L} = {L \times \frac{R_{2} - R_{1}}{R_{2} + R_{1}}}};} & (4)\end{matrix}$

Thus, the alignment shift AL between the bar-type conductive pad P₅₁ andthe first and second portions (D₁₁ and D₁₂) can be obtained if the firstresistance R₁ and the second resistance R₂ are measured. That is to say,alignment shift ΔL between the bar-type conductive P₅₁ and the first andsecond portions (D₁₁ and D₁₂) of the H-type deep trench capacitor iszero when the first resistance R₁ equals the second resistance R₂.

With reference to FIG. 3, the bar-type conductive pad P₅₁ is shifted bya distance ΔL along the direction DIR1 if the masks of the H-type deeptrench capacitor (D₁₁, D₁₂ and D₂₁) and the bar-type conductive pad P₅₁have an alignment shift ΔL in the direction DIR1. If this condition ismet, the first resistance R₁ is smaller than the second resistance R₂according to the equations 1 and 2. Moreover, the alignment shift ΔL canbe obtained according to the equation 4.

On the contrary, the bar-type conductive pad P₅₁ is shifted by adistance ΔL along the direction DIR2 if the masks of the H-type deeptrench capacitor (D₁₁, D₁₂ and D₂₁) and the bar-type conductive pad P₅₁have an alignment shift ΔL in the direction DIR2. If this condition ismet, the first resistance R₁ is larger than the second resistance R₂according to the equations 1 and 2. Moreover, the alignment shift can beobtained according to the equation 4.

In the present invention, the test device 200 disposed in the scribeline region and a plurality of memory cells with vertical transistors inthe memory region are formed simultaneously. For example, the deeptrench capacitors 102 of the memory cells in the memory region and theH-type deep trench capacitor (D₁₁, D₁₂ and D₂₁) in the active area A₁are formed simultaneously with the same masks, process and conditions.The word lines 118 a˜118 b of the memory cells in the memory region andthe first to fourth conductive pads P₁˜P₄ and the bar-type conductivepad P₅₁ are formed simultaneously with the same mask, process andconditions. Therefore, the memory region and the test device may havethe same alignment shift between deep trench capacitors (102, D₁₁ andD₁₂) and word lines (118 a˜118 d, P₁˜P₄ and P₅₁) use of the same maskand the same process. Thus, alignment of deep trench capacitors and wordlines in memory region can be obtained according to whether the firstresistance R₁ equals the second resistance R₂.

The present invention also provides a method for detecting alignment ofdeep trench capacitors and word lines in memory devices with verticaltransistors. In the method of the present invention, a wafer with atleast one scribe line region and at least one memory region is provided.

A plurality of memory cells with vertical transistors in the memoryregion and at least one test device in the scribe line region are formedsimultaneously, wherein the memory regions have deep trench capacitorsand word lines as shown in FIG. 1 and FIG. 2. The structure of the testdevice 200 is shown in FIG. 3. The deep trench capacitors 102 in thememory regions and the H-type deep trench capacitor (D₁₁, D₁₂ and D₂₁)in the test device are formed by the same mask and the same process. Theword line 118 a˜118 d in the memory regions and the first to fourthconductive pads (P₁˜P₄) and the bar-type conductive pad P₅₁ are formedby the same mask and the same process.

Next, a first resistance R₁ between the first conductive pad P₁ and thebar-type conductive pad P₅₁ is determined. A second resistance R₂between the second conductive pad P₂ and the bar-type conductive pad P₅₁is determined. Then, alignment of the H-type deep trench capacitor andthe bar-type conductive pad P₅₁ of the test device 200 is determinedaccording to whether the first resistance R₁ is equal to the secondresistance R₂.

The memory region and the test device may have the same alignment shiftbetween deep trench capacitors (102, D₁₁ and D₁₂) and word lines (118a˜118 d, P₁˜P₄ and P₅₁) use of the same masks and the same process.Thus, alignment of deep trench capacitors and word lines in memoryregion can be obtained according to whether the first resistance R₁equals the second resistance R₂. The alignment shift between deep trenchcapacitors and word lines in the memory regions can also be obtainedaccording to the equation 4.

Further, in the present invention the test device is disposed in thescribe line region to avoid occupying layout space.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A test device for detecting alignment of deep trench capacitors andword lines in DRAM devices with vertical transistors, wherein the testdevice is disposed in a scribe line region of a wafer, comprising: anactive area disposed in the scribe line region; an H-type deep trenchcapacitor disposed in the active area, having parallel first and secondportions and a third portion, wherein each of the first and secondportions has a center and two ends, and the third portion is disposedbetween the centers of the first and second portions; first to fourthconductive pads disposed on the two ends of the first and secondportions respectively; and a bar-type conductive pad disposed betweenthe first and second portions, having a center aligned with a center ofthe third portion.
 2. The test device as claimed in claim 1, wherein thefirst to fourth conductive pads and the bar-type conductive pad are madeof the same material.
 3. The test device as claimed in claim 1, whereinthe first to fourth conductive pads and the bar-type conductive pad aremade of polysilicon.
 4. The test device as claimed in claim 1, whereinthe bar-type conductive pad, the first portion and the second portionare parallel.
 5. A method for detecting alignment of deep trenchcapacitors and word lines in DRAM devices with vertical transistors,comprising: providing a wafer with at least one scribe line region andat least one memory region; forming a plurality of memory cells withvertical transistors in the memory region and at least one test devicein the scribe line region simultaneously, wherein the memory cells haveword line areas and deep trench capacitors, the test device including:an active area disposed in the scribe line region; an H-type deep trenchcapacitor disposed in the active area, having parallel first and secondportions and a third portion, wherein each of the first and secondportions has a center and two ends, and the third portion is disposedbetween the centers of the first and second portions; first to fourthconductive pads disposed on the two ends of the first and secondportions respectively; and a bar-type conductive pad disposed betweenthe first and second portions, having a center aligned with a center ofthe third portion; detecting a first resistance between the firstconductive pad disposed on the first portion and the bar-type conductivepad, and a second resistance between the second conductive pad disposedon the second portion and the bar-type conductive pad; determiningalignment of the H-type deep trench capacitor and the bar-typeconductive pad according to the first resistance and the secondresistance; and determining alignment of the deep trench capacitors andword lines in the memory region according to alignment of the H-typedeep trench capacitor and the bar-type conductive pad of the testdevice.
 6. The method as claimed in claim 5, wherein the bar-typeconductive pad is a predetermined distance from the first and secondportions.
 7. The method as claimed in claim 6, further comprising a stepof determining alignment shift (ΔL) of the H-type deep trench capacitorand the bar-type conductive pad according to the first resistance, thesecond resistance, and the predetermined distance between first andsecond portions and the bar-type conductive pad respectively.
 8. Themethod as claimed in claim 7, wherein the alignment shift (ΔL) isdetermined by an equation:${{\Delta\quad L} = {L \times \frac{\left( {{R2} - {R1}} \right)}{\left( {{R2} + {R1}} \right)}}};$wherein L is the predetermined distance between first and secondportions and the bar-type conductive pad respectively; R1 is the firstresistance between the first conductive pad disposed on the firstportion and the bar-type conductive pad; and R2 is the second resistancebetween the second conductive pad disposed on the second portion and thebar-type conductive pad.
 9. The method as claimed in claim 5, whereinthe first to fourth conductive pads and the bar-type conductive pad aremade by the same material.
 10. The method as claimed in claim 5, whereinthe first to fourth conductive pads and the bar-type conductive pad aremade of polysilicon.
 11. The method as claimed in claim 5, wherein thebar-type conductive pad, the first portion and the second portion areparallel.
 12. The method as claimed in claim 5, wherein the alignment ofthe H-type trench capacitor and the bar-type conductive pad is abnormalwhen the first resistance does not equal the second resistance.